https://icon.sourcearcade.org/tags/hardening/ Recent content in Hardening on icon Hugo en-us Nico Huber. All rights reserved Sat, 12 Sep 2026 23:32:00 +0200 https://icon.sourcearcade.org/posts/training-mode_boot_flow/ Sat, 12 Sep 2026 23:32:00 +0200 https://icon.sourcearcade.org/posts/training-mode_boot_flow/ <pre><code>Modern PCs run a lot of proprietary firmware on their main CPUs. In the past, it was sometimes possible to have all the initialisation steps in open-source, for instance with the coreboot firmware framework. At some point however, the initialisation process became more complex, and less documented. Then, alas, open-source firmware fell behind. A huge part of this complexity comes with the DRAM training. Modern DDR DRAM needs very precise timings, and the time a signal takes can differ from hardware unit to hardware unit. Hence, special algorithms are used to detect working timings at runtime. These timings are often stored in the firmware flash, and are picked up on subsequent boots. In coreboot, this is called MRC cache, named after Intel's Memory Reference Code. On AMD systems, the DRAM training and potentially more of the initiali- sation is done by firmware on an auxiliary processor. When the main x86 CPU comes out of reset, DRAM is already available. And thanks to AMD's openSIL effort, everything running on the x86 cores can be open-source again. The separation of the more complex, more proprietary steps from the initialisation that runs on the x86 seems to pay off. Let's explore a different separation that runs on a single processor and utilises the idea of cached training data as a barrier, the Training-Mode Boot Flow. </code></pre> <p>Open-source software is prevailing, because of its flexibility, transparency and trustworthiness. In firmware, OTOH, we still have proprietary components, often because of IP concerns. Mixing proprietary and open-source firmware components on a single boot path has several disadvantages.</p>